The transmission of information in digital form, whether in a baseband or a modulated format, requires the generation of a clock signal at the receiver to ensure accurate detection of the transmitted information. Devices that produce such a clock signal and synchronize it to the incoming data stream are referred to generally as bit synchronizers. For those data formats that do not have a spectral line component at the bit rate or any of its harmonics, it is necessary to somehow extract the clock signal from the incoming data stream. It is also desirable to design the bit synchronizer such that its operation is not limited to a single data frequency or rate, but rather is easily adaptable to different bit rates.
A prior art bit synchronizer is illustrated in FIG. 1. An incoming data stream is provided as an input to a low pass filter 10 for removing high-frequency noise and unwanted demodulation frequency components that may be present in the data stream. The low-pass filtered signal is input to a matched filter 12 for providing an output signal that is maximized at a particular time during each bit interval. Ideally, this maximization point is the mid-point of each bit interval.
To provide the synchronized clock signal for data decoding, the output signal from the matched filter 12 is input to a non-linear device 14; for example a square-law device such as a rectifier. The resultant signal is filtered by a bandpass filter 16 and baseline corrected in a baseline corrector 18 to compensate for any baseline drift. Because the bandpass filter 16 inherently provides ac coupling, the baseline corrector 18 is required to re-establish the baseline.
In conjunction with the bandpass filter 16 and the baseline corrector 18, a frequency component is generated at the bit rate (R). The corrected signal is then input to the phase-locked loop 19, including a phase detector 20, a loop filter 22, and a voltage controlled oscillator 24. In the phase detector 20 the corrected signal from the baseline corrector 18 and the local oscillator signal from the voltage controlled oscillator 24 are compared and a phase error signal (.theta..sub.E1) is generated for controlling the voltage controlled oscillator 24 via the loop filter 22. Specifically the phase detector 20 phase compares two signals A (the local oscillator signal) and B (the signal from the baseline corrector 18). Since the phase-locked loop 19 imparts a 90.degree. phase shift to the input signal, the phase detector 20 performs a comparison cos A.multidot.sin B=(1/2)(sin(A+B))+(1/2)(sin (A-B)). The resultant signal is filtered by the loop filter 22 and reduces to .theta..sub.E1 .perspectiveto.sin(A-B) for small phase errors. Thus as the phase of A approaches the phase of B,.theta..sub.E1 goes to zero, and the local oscillator signal, lacking a control signal, remains constant (in phase and frequency).
The local oscillator signal from the voltage controlled oscillator 24 is also input to a sampler 30 for controlling the sampler 30 such that bit decisions are made at each mid-bit interval, to minimize the bit error rate in the decoded data signal. The phase shifted signal from the 90.degree. phase shifter 26 should ideally be 90.degree. out of phase with the baseline corrected signal from the baseline corrector 18.
Specifically, the phase detector 28 phase compares two signals B (the signal from the baseline corrector 18) and C (the signal from the 90.degree. phase shifter 26). The comparison produces .theta..sub.E2 =cos B.multidot.cos C=(1/2)(cos(B+C))+(1/2)(cos(B-C)), which reduces to 1 as the phase of B approaches that of C. Thus the lock indicator produces a lock indication signal (i.e., a 1) when the phases of B and C are equal.
There are several disadvantages associated with this prior art design. For example, any device used as the non-linear device 14 will exhibit some temperature dependency. Also, if the prior art bit synchronizer is to be used in a multiple rate environment, it will be necessary to use a different 90.degree. phase shifter 26 for each rate and also a different bandpass filter 16 for each rate. As previously mentioned, the use of ac coupling requires inclusion of the baseline corrector 18. Lastly, it is necessary to use the matched filter 12 so that the non-linear device 14 will produce a sufficiently large component at the bit rate to which the phase locked loop 19 can lock.